Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization

نویسندگان

چکیده

In this article, we propose a carbon nanotube (CNT) field-effect transistor (CNFET)-based static random access memory (SRAM) design at the 5-nm technology node that is optimized based on tradeoff between performance, stability, and power efficiency. addition to size optimization, physical model parameters including CNT density, diameter, CNFET flat band voltage are evaluated for SRAM performance improvement. Optimized compared with state-of-the-art 7-nm FinFET cell Arizona State University [ASAP predictive models (PTM)] library. We find read, write EDPs, of proposed improved by 67.6%, 71.5%, 43.6%, respectively, cell, slightly better stability. interconnects both inside in-between cells considered compose an all-carbon-based (ACS) array which will be discussed in Part II article. A copper implemented used comparison.

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ژورنال

عنوان ژورنال: IEEE Transactions on Very Large Scale Integration Systems

سال: 2022

ISSN: ['1063-8210', '1557-9999']

DOI: https://doi.org/10.1109/tvlsi.2022.3146125